1. Field of the Invention
The present invention relates to a wiring board having a plurality of wiring layers, method forming a via in the wiring board, and a method of manufacturing the wiring board.
2. Description of the Related Art
As miniaturization of wiring patterns formed on wiring boards advances, and the rate of signal transmission increases, the influence of noise signals occurring between adjacent lines increases. To reduce such noise, a wiring board having a pair of signal lines (referred to as differential lines, hereinafter) for transmitting differential signals has been in practical use.
A wiring board having a plurality of wiring layers has a via formed for electrically connecting the wiring layers to each other. In the case where differential signals are transmitted, a pair of vias for differential lines is preferably formed (see Japanese Patent Laid-Open Nos. 2001-053397 and 2002-353588).
In the case where a high frequency signal at about 1 GHz or higher is transmitted, a via for a grounding line is preferably formed in the vicinity of the vias for the differential lines. The wiring board described in Japanese Patent Laid-Open Nos. 2001-053397 and 2002-353588 has a pair of vias for differential lines formed to penetrate through a region surrounded by a via used for a grounding line. With such a configuration, the wiring board is less likely to be affected by external noise.
When a pair of vias is formed close to each other in a wiring board, the vias are disposed so that the space between the lands for the vias is equal to or larger than a certain distance to prevent electrical short-circuits between the lands. In particular, the outermost wiring layer exposed on the surface of the wiring board is thicker than the other wiring layers because of the plating that is used to form the vias. Therefore, for the outermost layer of the wiring board, the space between the lands needs to be large in order to prevent dielectric breakdown. For example, the space between the lands needs to be equal to 120 μm-140 μm or larger.
Therefore, in the wiring boards described in Japanese Patent Laid-Open Nos. 2001-053397 and 2002-353588, there is a limit to reduction of the space between the vias.
When the space between the vias is large, there is a problem in which the electromagnetic coupling intensity of the differential signals transmitted through the differential lines will decrease, and in which it will be difficult to ensure signal integrity. In addition, when the space between the vias is large, there is a problem that the region in which the wiring pattern is to be formed (referred to simply as a wiring region, hereinafter) increases.